An attempt to hide the two different types of objects (Site and ClockRegion) from the view of the PBlockRange.
|AbstractModuleInst<ModuleT,PlacementT,T extends AbstractModuleInst<ModuleT,PlacementT,T>>
Created on: Jun 21, 2017
Stores a BEL attribute with the associated net.
A cell corresponds to the leaf cell within the logical netlist
and provides a mapping to a physical location BEL on the device.
Helper class to provide default static (GND or VCC) connection values to newly created cells.
The Design class is the central location that maintains the physical netlist and has hooks and references into the logical netlist.
A collection of methods to operate on
Parent DRC that executes a list of child DRCs, returning the sum of all failed checks.
Parses metadata file generated by the Tcl command in rapidwright.tcl/generate_metadata.
Allows RapidWright to read/write modules to a serialized, binary file.
A wrapper class for multiple implementations of a module.
A module instance with flexible implementation.
There is no direct representation of a module instance in Vivado.
A placement of a
This class represents the physical net to be routed (both inter-site and intra-site).
Represents a routing interface point that can be attached to a logical port or pin of a cell.
Class specifically created to manage pin swaps on the same site (such as LUTs) Created on: Nov 22, 2017
This class represents the ports used to define the interfaces of modules.
TileRectangle that is relocatable.
Generates Verilog or VHDL stub files to instantiate design checkpoint files.
TileRectangle that uses Row/Column indices for storage.
Represents a site and keeps tracks of attributes on its BELs.
This class represents the instance of a site as configured by the user design.
This class represents the site pin sources and sinks in a physical net.
A Rectangle of tiles, i.e.
Captures unisim property values with associated Vivado types.
This enum is simply a way to check net types easier than using Strings.
Created on: May 10, 2016
Generated on: Fri Oct 20 23:25:44 2023 by: com.xilinx.rapidwright.release.UnisimParser Enumerates supported Unisim primitives that map to Xilinx devices.
Enumerates the Type of properties found when querying Vivado objects with report_property.