Generates a placed and routed adder or subtractor using CLB LUTs, CARRY8s and flip flops.
Serves as a parent class for
Takes as input two DCP files, one with an MMCM in one DCP that is to be copied into another DCP.
A simple netlist creation example (no placement and routing information included).
Created on: May 24, 2019
Example of building a minimum viable design in RapidWright without RTL.
|PicoBlazeArray.PicoBlazeArrayCreator<T extends AbstractModuleInst<?,?,T>>|
Generates a delay of
Generates a delay of "depth" cycles for a bus of "width" w using flip flops.
This example enumerates all cell instances in an EDIF netlist and writes them to a file.
Given an input DCP, a hierarchy prefix (empty string to match entire design) and tile column/row offsets, move all matching cells (and the PIPs that connect between such cells) by this tile offset.
Basic example to show reading in a placed and routed DCP and calculating the worst case data path delay.
Small example that illustrates how to invoke the SAT router to route a small area of a design by providing a fully placed DCP and a pblock area constraint to the router.
Highly parameterizable SLR bridge crossing circuit generator for UltraScale+ devices.
Creates a zoomable UI view of a provided TileScene
Example of how to invoke SAT Router to replace failed routing run.