Take a unrouted or partially routed design, route it in Vivado with auto generated timing constraints to find
the maximum clock frequency the design supports.
The minimum clock period is found via a three-stage approach, where each stage consists of a number of Vivado runs:
Route at user-provided frequency
Calculate new period a bit tighter than what was achieved. In 0.05ns increments, schedule runs around that center
Search between the best result where the constraints were met and the best result where the constraints were not met. This schedules runs in 0.002ns increments
The number of runs can be quite large, so using LSF is recommended.
This tool only changes timing constraints of one user-specified clock input. Other clocks should already have
timing constraints assigned to them before passing the design to this tool.