Edges within a TimingGraph that encapsulate logic delays, net delays, and debug information.
A TimingGraph is an acyclic weighted-directed graph representing logic delays and physical net delays based on analyzing the circuits within
A TimingGroup is our main hardware abstraction proposed by our FPT'19 paper: a TimingGroup abstracts over a set of connected PIPs, Nodes, and pins in order to create a coarser grain unit for which we calculate the delay.
A TimingManager sets up and creates an example TimingModel and an example TimingGraph for a given Design.
A TimingModel calculates net delay by implementing the lightweight timing model described in our FPT'19 paper.
A TimingVertex represents a node within the TimingGraph.
The current set of TimingGroup types including types for each of the basic wire length types, bounces, pin types, and other.
Example distance categories that we created to describe some example filtering options for TimingGroups.
The direction for the TimingGroup, which is basically either horizontal or vertical.
Compass directions that are used in the naming convention for wires to represent their directions.