Generates a placed and routed adder or subtractor using CLB LUTs, CARRY8s and flip flops.
Takes as input two DCP files, one with an MMCM in one DCP that is to be copied into another DCP.
A simple netlist creation example (no placement and routing information included).
Created on: May 24, 2019
Example of building a minimum viable design in RapidWright without RTL.
Generates a delay of
Generates a delay of "depth" cycles for a bus of "width" w using flip flops.
This example enumerates all cell instances in an EDIF netlist and writes them to a file.
Basic example to show reading in a placed and routed DCP and calculating the worst case data path delay.
Small example that illustrates how to invoke the SAT router to route a small area of a design by providing a fully placed DCP and a pblock area constraint to the router.
Highly parameterizable SLR bridge crossing circuit generator for UltraScale+ devices.
Example of how to invoke SAT Router to replace failed routing run.