Package com.xilinx.rapidwright.device

Interface Summary

Interface	Description
WireInterface	An interface to enable methods to operate on the common methods of a Wire object as well as a Node object.

Class Summary

Class	Description
BEL	This class represents the canonical representation of a BEL (Basic Element of Logic), or a RBEL (Routing BEL), or a site port.
BELPin	Represents a pin on an element, including a site port where this pin corresponds to a site pin.
ClockRegion	Represents a clock region (a rectangular group of tiles on a device) that has shared clocking resources.
Device	This is the main class that stores information about Xilinx devices.
DeviceTools
EnumerateIOExpansions
Grade	Object to keep track of different speed and temperature grades for a device.
IOBank
Node	This class represents a reference to the notion of a node in Vivado, which is an electrically connected set of Wires that can span tiles.
Package	Represents an instance of a specific package for a part.
PackagePin	Holds data for a package pin and its mapping to a specific site/bel.
Part	Generated on: Wed Jun 11 09:41:43 MDT 2025 by: com.xilinx.rapidwright.release.PartNamePopulator Class used to uniquely represent a Xilinx part.
PartNameTools	Generated on: Wed Jun 11 09:41:43 MDT 2025 by: com.xilinx.rapidwright.release.PartNamePopulator Class to hold utility APIs dealing with Parts and device names.
PIP	This class represents the programmable-interconnect-points (PIPs) as found in Vivado designs.
PIPWires	Simple pair of ints that act as the start and end wire of a prototype PIP.
PseudoPIPHelper	Helper class for pseudo PIP types and getting site use information.
Site	This class represents a site, a logic hierarchy level that is below a tile and generally contains one or more BELs.
SitePin	A light-weight object to allow references to a site and pin Created on: Jul 5, 2016
SitePIP	Represents the arcs present in routing BELs (RBELs) in Sites.
SLR	This class represents a super logic region, or a die within a device.
Tile	Tiles are one of basic building blocks of Xilinx FPGAs.
Wire	This class represents the device object called a wire in Vivado.

Enum Summary

Enum	Description
BELClass	Differentiates different types of BELs (Basic Elements of Logic).
BELPin.Direction	BEL Pin directions
FamilyType	Generated on: Wed Jun 11 09:41:43 MDT 2025 by: com.xilinx.rapidwright.release.PartNamePopulator Set of all Supported Xilinx families in RapidWright
IntentCode	List of wire/node annotations available on devices in Vivado.
IOBankType	Generated on: Thu Nov 21 13:34:08 MST 2024 by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater Enumeration of IOBankType type for all valid devices within Vivado.
IOStandard	Generated on: Thu Nov 21 13:34:08 MST 2024 by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater Enumeration of IOStandard type for all valid devices within Vivado.
PIPType	This type captures the PIP properties shown in a Vivado PIP called "IS_BUFFERED_2_0", "IS_BUFFERED_2_1" and "IS_DIRECTIONAL"
Series	Xilinx Architecture Series or Generations.
SitePIPStatus	Different modes for site PIPs.
SiteTypeEnum	Generated on: Sat Jun 07 22:31:12 MDT 2025 by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater Enumeration of SiteTypeEnum type for all valid devices within Vivado.
TileTypeEnum	Generated on: Sat Jun 07 22:31:12 MDT 2025 by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater Enumeration of TileTypeEnum type for all valid devices within Vivado.