com.xilinx.rapidwright.design.tools

Class NetlistClockDetection

Object

com.xilinx.rapidwright.design.tools.NetlistClockDetection

public class NetlistClockDetection
extends Object

Finds all terminal hierarchical port insts (pins) which either drive a given hierarchical net through only combinational logic or which gate the driving of that net through sequential logic. When any of these pins encounter a change of value, the hierarchical net's value may change. These pins can be considered gating drivers and/or likely terminal clock signal pins for the input hierarchical net.

Field Summary

Fields

Modifier and Type	Field and Description
static Map<Series,Map<String,Set<String>>>	seriesPrimsToClockPins A map whose keys are FPGA series and whose values are maps from the names of those series' primitives which have clock input pins to those clock input pins.

Constructor Summary

Constructors

Constructor and Description
NetlistClockDetection()

Method Summary

Modifier and Type	Method and Description
static Set<EDIFHierPortInst>	getGatingDrivers(EDIFHierNet hNet, Series series) Finds all terminal hierarchical port insts (pins) which gate changes to the given hierarchical net's value, i.e., finds all terminal pins which may be drivers of the net through non-clocked primitives and all likely terminal clock signal pins that gate signals which drive the net through clocked primitives.
static Map<String,Set<String>>	getPrimsToClockPins(Series series) Gets a map from the names of an FPGA series' primitives which have clock input pins to those clock input pins.
static void	main(String[] args)

Methods inherited from class Object

equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

seriesPrimsToClockPins

public static Map<Series,Map<String,Set<String>>> seriesPrimsToClockPins

A map whose keys are FPGA series and whose values are maps from the names of those series' primitives which have clock input pins to those clock input pins.

Constructor Detail

NetlistClockDetection

public NetlistClockDetection()

Method Detail

getPrimsToClockPins

public static Map<String,Set<String>> getPrimsToClockPins(Series series)

Gets a map from the names of an FPGA series' primitives which have clock input pins to those clock input pins.

getGatingDrivers

public static Set<EDIFHierPortInst> getGatingDrivers(EDIFHierNet hNet,
                                                     Series series)

Finds all terminal hierarchical port insts (pins) which gate changes to the given hierarchical net's value, i.e., finds all terminal pins which may be drivers of the net through non-clocked primitives and all likely terminal clock signal pins that gate signals which drive the net through clocked primitives. For example, when run on the output hierarchical net of a LUT2 whose inputs come from a flop and a LUT, this will return the terminal hierarchical port inst(s) driving the flop's clock pin as well as any gating drivers of the input LUT's inputs, determined recursively.

Parameters:

hNet - The hierarchical net to find gating drivers of.

series - The FPGA series that the containing netlist targets.

main

public static void main(String[] args)