public class NetlistClockDetection
extends Object
| Modifier and Type | Field and Description |
|---|---|
static Map<Series,Map<String,Set<String>>> |
seriesPrimsToClockPins
A map whose keys are FPGA series and whose values are maps from the names of
those series' primitives which have clock input pins to those clock input pins.
|
| Constructor and Description |
|---|
NetlistClockDetection() |
| Modifier and Type | Method and Description |
|---|---|
static Set<EDIFHierPortInst> |
getGatingDrivers(EDIFHierNet hNet,
Series series)
Finds all terminal hierarchical port insts (pins) which gate changes to the given
hierarchical net's value, i.e., finds all terminal pins which may be drivers of
the net through non-clocked primitives and all likely terminal clock signal pins
that gate signals which drive the net through clocked primitives.
|
static Map<String,Set<String>> |
getPrimsToClockPins(Series series)
Gets a map from the names of an FPGA series' primitives which have clock input
pins to those clock input pins.
|
static void |
main(String[] args) |
public static Map<Series,Map<String,Set<String>>> seriesPrimsToClockPins
public static Map<String,Set<String>> getPrimsToClockPins(Series series)
public static Set<EDIFHierPortInst> getGatingDrivers(EDIFHierNet hNet, Series series)
hNet - The hierarchical net to find gating drivers of.series - The FPGA series that the containing netlist targets.public static void main(String[] args)