An attempt to hide the two different types of objects (Site and ClockRegion) from the view of the PBlockRange.
A cell corresponds to the leaf cell within the logical netlist
The Design class is the central location that maintains the physical netlist and has hooks and references into the logical netlist.
A collection of methods to operate on
Parses metadata file generated by the Tcl command in rapidwright.tcl/generate_metadata.
Allows RapidWright to read/write modules to a serialized, binary file.
A wrapper class for multiple implementations of a module.
There is no direct representation of a module instance in Vivado.
This class represents the physical net to be routed (both inter-site and intra-site).
Class specifically created to manage pin swaps on the same site (such as LUTs) Created on: Nov 22, 2017
This class represents the ports used to define the interfaces of modules.
Generates Verilog or VHDL stub files to instantiate design checkpoint files.
This class represents the instance of a site as configured by the user design.
This class represents the site pin sources and sinks in a physical net.
This enum is simply a way to check net types easier than using Strings.
Created on: May 10, 2016
Generated on: Wed Jun 19 13:05:03 2019 by: com.xilinx.rapidwright.release.UnisimParser Enumerates supported Unisim primitives that map to Xilinx devices.