================ Glossary ================ .. glossary:: :sorted: Laguna When a device is composed of multiple dies (using :term:`SSIT`), CLBs are replaced with Laguna Tiles and Sites to provided dedicated logic to crossing from one die to the next. Laguna sites contain dedicated RX and TX flip flops that connect to :term:`SLLs`. SLL Super long line, these are the wires that cross between dies in a multi-die device (see :term:`SSIT`). SLR Super logic region, in multi-die devices, each super logic region is one die connected to other die via an interposer. The routing wires that connect these SLRs are :term:`SLLs`). Also see :ref:`SLR (Super Logic Region)`. SSIT Stacked silicon interconnect technology: Xilinx uses an interposer substrate to package multiple FPGA die into a single package. Shell A static FPGA design that provides a common interface to off-chip resources (DDR, PCIe,...) intended for multiple applications. Tile Pattern A sequence of tile types. For example, the 7 series device family have four types of CLB tiles (CLBLL_L, CLBLL_R, CLBM_R, CLBM_L). A PBlock can cover several tile columns, thus spaning several heterogeneous tile types. If the logic implemented within the pblock is relocated on the device, it must use the same tile pattern, meaning sequence of CLB tile types must match.